From c9583f40551a39705a8c057a3ff694997b3b1c2e Mon Sep 17 00:00:00 2001 From: Lindgren Date: Fri, 28 Mar 2025 10:43:59 +0100 Subject: [PATCH] Updates to NVM handling * Remove generated rte write for type2 nvm signals due to risks * Removed unnecessary SetRamBlockStatus calls * Meaning nvmPortPattern can be removed * Updated RTE dummy Change-Id: I1ddc960b13014501d2d3a7a0913119249660d8b9 --- NOTICE | 43 ++++++------------- docs/project_config.md | 5 --- powertrain_build/build_proj_config.py | 1 - powertrain_build/nvm_def.py | 54 +++++++++--------------- powertrain_build/rte_dummy.py | 13 ------ tests/powertrain_build/test_nvm_def.py | 8 +--- tests/powertrain_build/test_rte_dummy.py | 25 ----------- 7 files changed, 34 insertions(+), 115 deletions(-) diff --git a/NOTICE b/NOTICE index 7e97d43..8427d94 100644 --- a/NOTICE +++ b/NOTICE @@ -12,9 +12,9 @@ Notices Report Content Components: -Coverage 7.7.1: http://nedbatchelder.com/code/modules/coverage.html : Apache License 2.0 +Coverage 7.8.0: http://nedbatchelder.com/code/modules/coverage.html : Apache License 2.0 exceptiongroup 1.2.2: https://github.com/python-trio/exceptiongroup : MIT License -flake8 7.1.2: https://gitlab.com/pycqa/flake8 : MIT License +flake8 7.2.0: https://gitlab.com/pycqa/flake8 : MIT License gitdb 4.0.12: http://github.com/gitpython-developers/gitdb : BSD 3-clause "New" or "Revised" License GitPython 3.1.44: https://github.com/gitpython-developers/GitPython : BSD 3-clause "New" or "Revised" License idna 3.10: https://github.com/kjd/idna : BSD 3-clause "New" or "Revised" License @@ -23,8 +23,8 @@ NumPy 1.24.4: https://numpy.org/ : BSD 3-clause "New" or "Revised" License Packaging 24.2: https://github.com/pypa/packaging : (BSD 2-clause "Simplified" License OR Apache License 2.0) pbr 6.1.1: http://openstack.org : Apache License 2.0 psf-requests 2.32.3: http://docs.python-requests.org : Apache License 2.0 -pycodestyle 2.12.1: https://pypi.python.org/pypi/pycodestyle : MIT License -Pyflakes 3.2.0: https://github.com/pyflakes/pyflakes : MIT License +pycodestyle 2.13.0: https://pypi.python.org/pypi/pycodestyle : MIT License +Pyflakes 3.3.2: https://github.com/pyflakes/pyflakes : MIT License pypi/setuptools 59.6.0: https://pypi.org/project/setuptools/ : MIT License pytest 8.3.5: http://pytest.org : MIT License python3-charset-normalizer 3.4.1: https://github.com/ousret/charset_normalizer : MIT License @@ -41,14 +41,14 @@ voluptuous 0.15.2: http://pypi.python.org/pypi/voluptuous : BSD 3-clause "New" o Copyright Text: -Coverage 7.7.1 pypi:coverage/7.7.1: http://nedbatchelder.com/code/modules/coverage.html +Coverage 7.8.0 pypi:coverage/7.8.0: http://nedbatchelder.com/code/modules/coverage.html No Copyrights found exceptiongroup 1.2.2 pypi:exceptiongroup/1.2.2: https://github.com/python-trio/exceptiongroup Copyright (c) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, Copyright (c) 2022 Alex Gr -flake8 7.1.2 pypi:flake8/7.1.2: https://gitlab.com/pycqa/flake8 +flake8 7.2.0 pypi:flake8/7.2.0: https://gitlab.com/pycqa/flake8 No Copyrights found gitdb 4.0.12 pypi:gitdb/4.0.12: http://github.com/gitpython-developers/gitdb (c) @@ -2681,29 +2681,10 @@ psf-requests 2.32.3 pypi:requests/2.32.3: http://docs.python-requests.org copyright: (c) 2017 by Kenneth Reitz. -pycodestyle 2.12.1 pypi:pycodestyle/2.12.1: https://pypi.python.org/pypi/pycodestyle - Copyright (C) 2006-2009 Johann C. Rocholl - - Copyright (C) 2009-2014 Florent Xicluna - - Copyright (C) 2014-2016 Ian Lee - - Copyright © 2006-2009 Johann C. Rocholl - - Copyright © 2009-2014 Florent Xicluna - - Copyright © 2014-2020 Ian Lee - -Pyflakes 3.2.0 pypi:pyflakes/3.2.0: https://github.com/pyflakes/pyflakes - Copyright 2005-2011 Divmod, Inc. - - Copyright 2013 Florent Xicluna. See LICENSE file for details -import os.path - -try: - - Copyright 2013-2014 Florent Xicluna - +pycodestyle 2.13.0 pypi:pycodestyle/2.13.0: https://pypi.python.org/pypi/pycodestyle + No Copyrights found +Pyflakes 3.3.2 pypi:pyflakes/3.3.2: https://github.com/pyflakes/pyflakes + No Copyrights found pypi/setuptools 59.6.0 pypi:setuptools/59.6.0: https://pypi.org/project/setuptools/ (c) *output } @@ -13653,7 +13634,7 @@ modification, are permitted provided that the following conditions are met: Licenses: Apache License 2.0 -(Coverage 7.7.1, Packaging 24.2, pbr 6.1.1, psf-requests 2.32.3) +(Coverage 7.8.0, Packaging 24.2, pbr 6.1.1, psf-requests 2.32.3) Apache License Version 2.0, January 2004 @@ -13957,7 +13938,7 @@ IN THE SOFTWARE --- MIT License -(exceptiongroup 1.2.2, flake8 7.1.2, pycodestyle 2.12.1, Pyflakes 3.2.0, pytest 8.3.5, python-pluggy 1.5.0, python3-charset-normalizer 3.4.1, RonnyPfannschmidt/iniconfig 2.1.0, ruamel-yaml 0.18.6, ruamel.yaml.clib 0.2.12, tomli 2.2.1, urllib3 2.3.0) +(exceptiongroup 1.2.2, flake8 7.2.0, pycodestyle 2.13.0, Pyflakes 3.3.2, pytest 8.3.5, python-pluggy 1.5.0, python3-charset-normalizer 3.4.1, RonnyPfannschmidt/iniconfig 2.1.0, ruamel-yaml 0.18.6, ruamel.yaml.clib 0.2.12, tomli 2.2.1, urllib3 2.3.0) The MIT License =============== diff --git a/docs/project_config.md b/docs/project_config.md index 7e70ef4..06a5811 100644 --- a/docs/project_config.md +++ b/docs/project_config.md @@ -352,7 +352,6 @@ when building with conan. "includeShared": false, "includeDiagnostics": true, "includeNvm": true, - "nvmPortPattern": "PS_LVCSC_SwcNv_{NvName}", "scaleMapsAndCurves": false } } @@ -428,10 +427,6 @@ Default is True. Include non-volatile memory elements or not. Default is True. -#### nvmPortPattern - -Port naming format string for NVM ports. - #### scaleMapsAndCurves Include slope and bias to MAP and CURVE data types or not. diff --git a/powertrain_build/build_proj_config.py b/powertrain_build/build_proj_config.py index af2b1f9..e07e3da 100644 --- a/powertrain_build/build_proj_config.py +++ b/powertrain_build/build_proj_config.py @@ -268,7 +268,6 @@ class BuildProjConfig: 'includeShared': file_config.get('includeShared', True), 'includeDiagnostics': file_config.get('includeDiagnostics', True), 'includeNvm': file_config.get('includeNvm', True), - 'nvmPortPattern': file_config.get('nvmPortPattern', None), 'scaleMapsAndCurves': file_config.get('scaleMapsAndCurves', True), } composition_name = file_config.get("compositionName", None) diff --git a/powertrain_build/nvm_def.py b/powertrain_build/nvm_def.py index ae1d07d..edf2021 100644 --- a/powertrain_build/nvm_def.py +++ b/powertrain_build/nvm_def.py @@ -650,11 +650,6 @@ class ZCNVMDef(NVMDef): def _append_nvm_rte_function_calls(self): """Append the NVM RTE function calls to the NVM config source file.""" - nvm_port_pattern = self._project_config.get_composition_config("nvmPortPattern") - if self.valid_nvm_definitions and nvm_port_pattern is None: - self.critical("NVM port pattern not defined in ProjectCfg.json. Cannot add NVM RTE function calls.") - return - init_function_lines = [ f'#include "{bd.CVC_CODE_ASIL_D_START}"\n' f"{self.init_function} {{\n", @@ -670,45 +665,38 @@ class ZCNVMDef(NVMDef): f'#include "{bd.CVC_CODE_ASIL_D_END}"\n', ] - error_status = [] main_function_lines = [] for nvm_name, nvm_data in self.valid_nvm_definitions.items(): - if nvm_data["method"] == "DIRECT-CALL": - pim_call = f"Rte_Pim_{nvm_name}()" - function_prefix = f"Rte_Call_{nvm_port_pattern.format(NvName=nvm_name)}" - main_function_lines.append(f" *{pim_call} = {nvm_name.lower()};\n") - if nvm_data["type"] == "type1": - init_function_lines.append(f" {function_prefix}_SetRamBlockStatus(TRUE);\n") + if nvm_data["type"] not in ["type1", "type2"]: + self.critical(f"Unknown NVM type: {nvm_data['type']} for NVM: {nvm_name}") + continue + if nvm_data["method"] not in ["DIRECT-CALL", "NVSWCOMPONENT"]: + self.critical(f"Unknown NVM method: {nvm_data['method']} for NVM: {nvm_name}") + continue + + if nvm_data["type"] == "type2": + self.warning( + f'{nvm_name.lower()} is a type2 {nvm_data["method"]}. Due to inherent risk type2 write calls are ' + 'not generated automatically, they have to be written manually and added to source code.' + ) + main_function_lines.append( + f" // Nvm {nvm_name.lower()} is type 2, add call in manually written source code.\n" + ) + elif nvm_data["type"] == "type1": + if nvm_data["method"] == "DIRECT-CALL": + pim_call = f"Rte_Pim_{nvm_name}()" + main_function_lines.append(f" *{pim_call} = {nvm_name.lower()};\n") init_function_lines.append(f" {nvm_name.lower()} = *{pim_call};\n") - elif nvm_data["type"] == "type2": - error_status = [" UInt8 errorStatus = 0;\n"] - main_function_lines.extend([ - f" {function_prefix}_GetErrorStatus(&errorStatus);\n", - " if (errorStatus == 0) {\n", - f" {function_prefix}_WriteBlock({pim_call});\n", - " }\n", - ]) - else: - self.critical(f"Unknown NVM type: {nvm_data['type']} for NVM: {nvm_name}") - elif nvm_data["method"] == "NVSWCOMPONENT": - if nvm_data["type"] == "type1": + elif nvm_data["method"] == "NVSWCOMPONENT": init_function_lines.append( f" Rte_Read_{nvm_name.upper()}_{nvm_name.upper()}(&{nvm_name.lower()});\n" ) main_function.append( f" Rte_Write_{nvm_name.upper()}_{nvm_name.upper()}(&{nvm_name.lower()});\n" ) - elif nvm_data["type"] == "type2": - self.warning( - f'{nvm_name.lower()} is a type2 NVSWCOMPONENT. Due to inherent risk type2 write calls are not ' - 'generated automatically, they have to be written manually and added to source code.' - ) - main_function_lines.append( - f" // Nvm {nvm_name.lower()} is type 2, add call in manually written source code.\n" - ) - output = init_function_lines + footer + ["\n"] + main_function + error_status + main_function_lines + footer + output = init_function_lines + footer + ["\n"] + main_function + main_function_lines + footer with open(self._file_name + ".c", mode="a", encoding="utf-8") as cptr: cptr.writelines(output) diff --git a/powertrain_build/rte_dummy.py b/powertrain_build/rte_dummy.py index 5167c0a..073db14 100644 --- a/powertrain_build/rte_dummy.py +++ b/powertrain_build/rte_dummy.py @@ -29,10 +29,6 @@ class RteDummy(ProblemLogger): self.nvm_def = nvm_def self.header_file_name = "Rte_Type" self.source_file_name = "Rte_Dummy" - nvm_port_pattern = self.build_cfg.get_composition_config("nvmPortPattern") - if nvm_port_pattern is None: - nvm_port_pattern = "{NvName}" - self.nvm_port_pattern = nvm_port_pattern def _get_header_header(self): """Get header for the RTE dummy header.""" @@ -89,12 +85,7 @@ class RteDummy(ProblemLogger): for memory_area in self.nvm_def._nvm_memory_areas: nvm_name = f"{prefix}{memory_area}" struct_name = f"dt_{nvm_name}" if use_rte_nvm_structs else f"struct {nvm_name}" - function_prefix = f"Rte_Call_{self.nvm_port_pattern.format(NvName=nvm_name)}" function_declarations.append(f"{struct_name} *Rte_Pim_{nvm_name}(void);") - - function_declarations.append(f"void {function_prefix}_SetRamBlockStatus(UInt8 status);") - function_declarations.append(f"void {function_prefix}_GetErrorStatus(UInt8 *status);") - function_declarations.append(f"void {function_prefix}_WriteBlock({struct_name} *block);") function_declarations.append(f"void Rte_Read_{nvm_name.upper()}_{nvm_name.upper()}({struct_name} *block);") function_declarations.append(f"void Rte_Write_{nvm_name.upper()}_{nvm_name.upper()}({struct_name} *block);") @@ -132,11 +123,7 @@ class RteDummy(ProblemLogger): for memory_area in self.nvm_def._nvm_memory_areas: nvm_name = f"{prefix}{memory_area}" struct_name = f"dt_{nvm_name}" if use_rte_nvm_structs else f"struct {nvm_name}" - function_prefix = f"Rte_Call_{self.nvm_port_pattern.format(NvName=nvm_name)}" lines_to_write.append(f"{struct_name} *Rte_Pim_{nvm_name}(void) {{ return ({struct_name} *)0; }}") - lines_to_write.append(f"void {function_prefix}_SetRamBlockStatus(UInt8 status) {{}}") - lines_to_write.append(f"void {function_prefix}_GetErrorStatus(UInt8 *status) {{}}") - lines_to_write.append(f"void {function_prefix}_WriteBlock({struct_name} *block) {{}}") lines_to_write.append(f"void Rte_Read_{nvm_name.upper()}_{nvm_name.upper()}({struct_name} *block) {{}}") lines_to_write.append(f"void Rte_Write_{nvm_name.upper()}_{nvm_name.upper()}({struct_name} *block) {{}}") lines_to_write.append("") diff --git a/tests/powertrain_build/test_nvm_def.py b/tests/powertrain_build/test_nvm_def.py index 0c32a2b..d5baa11 100644 --- a/tests/powertrain_build/test_nvm_def.py +++ b/tests/powertrain_build/test_nvm_def.py @@ -722,20 +722,14 @@ class TestZCNVMDef(unittest.TestCase): expected = [ '#include "CVC_CODE_ASIL_D_START.h"\nvoid VcNvmInit(void) {\n', " //Call this function in the SWC init runnable\n", - " Rte_Call_Dummy_NVM_LIST_8_SetRamBlockStatus(TRUE);\n", " nvm_list_8 = *Rte_Pim_NVM_LIST_8();\n", "}\n", '#include "CVC_CODE_ASIL_D_END.h"\n', "\n", '#include "CVC_CODE_ASIL_D_START.h"\nvoid VcNvm(void) {\n', " //Call this function in the SWC main runnable\n", - " UInt8 errorStatus = 0;\n", " *Rte_Pim_NVM_LIST_8() = nvm_list_8;\n", - " *Rte_Pim_NVM_LIST_16() = nvm_list_16;\n", - " Rte_Call_Dummy_NVM_LIST_16_GetErrorStatus(&errorStatus);\n", - " if (errorStatus == 0) {\n", - " Rte_Call_Dummy_NVM_LIST_16_WriteBlock(Rte_Pim_NVM_LIST_16());\n", - " }\n", + " // Nvm nvm_list_16 is type 2, add call in manually written source code.\n", "}\n", '#include "CVC_CODE_ASIL_D_END.h"\n' ] diff --git a/tests/powertrain_build/test_rte_dummy.py b/tests/powertrain_build/test_rte_dummy.py index 7ce85ee..3e8f73a 100644 --- a/tests/powertrain_build/test_rte_dummy.py +++ b/tests/powertrain_build/test_rte_dummy.py @@ -13,7 +13,6 @@ from powertrain_build.rte_dummy import RteDummy def mock_get_composition_config(key): """Function to mock BuildProjConfig.get_composition_config.""" return { - "nvmPortPattern": "PS_DUMMY_SwcNv_{NvName}", "compositionName": "testName", "softwareComponentName": "testName_SC", }[key] @@ -92,15 +91,9 @@ class TestRteDummy(unittest.TestCase): ( # header content "\n" "struct DUMMY_NVM_LIST_8 *Rte_Pim_DUMMY_NVM_LIST_8(void);\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_8_SetRamBlockStatus(UInt8 status);\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_8_GetErrorStatus(UInt8 *status);\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_8_WriteBlock(struct DUMMY_NVM_LIST_8 *block);\n" "void Rte_Read_DUMMY_NVM_LIST_8_DUMMY_NVM_LIST_8(struct DUMMY_NVM_LIST_8 *block);\n" "void Rte_Write_DUMMY_NVM_LIST_8_DUMMY_NVM_LIST_8(struct DUMMY_NVM_LIST_8 *block);\n" "struct DUMMY_NVM_LIST_16 *Rte_Pim_DUMMY_NVM_LIST_16(void);\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_16_SetRamBlockStatus(UInt8 status);\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_16_GetErrorStatus(UInt8 *status);\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_16_WriteBlock(struct DUMMY_NVM_LIST_16 *block);\n" "void Rte_Read_DUMMY_NVM_LIST_16_DUMMY_NVM_LIST_16(struct DUMMY_NVM_LIST_16 *block);\n" "void Rte_Write_DUMMY_NVM_LIST_16_DUMMY_NVM_LIST_16(struct DUMMY_NVM_LIST_16 *block);" ), @@ -117,15 +110,9 @@ class TestRteDummy(unittest.TestCase): ), ( # source content "struct DUMMY_NVM_LIST_8 *Rte_Pim_DUMMY_NVM_LIST_8(void) { return (struct DUMMY_NVM_LIST_8 *)0; }\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_8_SetRamBlockStatus(UInt8 status) {}\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_8_GetErrorStatus(UInt8 *status) {}\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_8_WriteBlock(struct DUMMY_NVM_LIST_8 *block) {}\n" "void Rte_Read_DUMMY_NVM_LIST_8_DUMMY_NVM_LIST_8(struct DUMMY_NVM_LIST_8 *block) {}\n" "void Rte_Write_DUMMY_NVM_LIST_8_DUMMY_NVM_LIST_8(struct DUMMY_NVM_LIST_8 *block) {}\n" "struct DUMMY_NVM_LIST_16 *Rte_Pim_DUMMY_NVM_LIST_16(void) { return (struct DUMMY_NVM_LIST_16 *)0; }\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_16_SetRamBlockStatus(UInt8 status) {}\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_16_GetErrorStatus(UInt8 *status) {}\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_16_WriteBlock(struct DUMMY_NVM_LIST_16 *block) {}\n" "void Rte_Read_DUMMY_NVM_LIST_16_DUMMY_NVM_LIST_16(struct DUMMY_NVM_LIST_16 *block) {}\n" "void Rte_Write_DUMMY_NVM_LIST_16_DUMMY_NVM_LIST_16(struct DUMMY_NVM_LIST_16 *block) {}\n" ) @@ -169,15 +156,9 @@ class TestRteDummy(unittest.TestCase): " UInt16 unused[1];\n" "} dt_DUMMY_NVM_LIST_16;\n\n" "dt_DUMMY_NVM_LIST_8 *Rte_Pim_DUMMY_NVM_LIST_8(void);\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_8_SetRamBlockStatus(UInt8 status);\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_8_GetErrorStatus(UInt8 *status);\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_8_WriteBlock(dt_DUMMY_NVM_LIST_8 *block);\n" "void Rte_Read_DUMMY_NVM_LIST_8_DUMMY_NVM_LIST_8(dt_DUMMY_NVM_LIST_8 *block);\n" "void Rte_Write_DUMMY_NVM_LIST_8_DUMMY_NVM_LIST_8(dt_DUMMY_NVM_LIST_8 *block);\n" "dt_DUMMY_NVM_LIST_16 *Rte_Pim_DUMMY_NVM_LIST_16(void);\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_16_SetRamBlockStatus(UInt8 status);\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_16_GetErrorStatus(UInt8 *status);\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_16_WriteBlock(dt_DUMMY_NVM_LIST_16 *block);\n" "void Rte_Read_DUMMY_NVM_LIST_16_DUMMY_NVM_LIST_16(dt_DUMMY_NVM_LIST_16 *block);\n" "void Rte_Write_DUMMY_NVM_LIST_16_DUMMY_NVM_LIST_16(dt_DUMMY_NVM_LIST_16 *block);" ), @@ -194,15 +175,9 @@ class TestRteDummy(unittest.TestCase): ), ( # source content "dt_DUMMY_NVM_LIST_8 *Rte_Pim_DUMMY_NVM_LIST_8(void) { return (dt_DUMMY_NVM_LIST_8 *)0; }\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_8_SetRamBlockStatus(UInt8 status) {}\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_8_GetErrorStatus(UInt8 *status) {}\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_8_WriteBlock(dt_DUMMY_NVM_LIST_8 *block) {}\n" "void Rte_Read_DUMMY_NVM_LIST_8_DUMMY_NVM_LIST_8(dt_DUMMY_NVM_LIST_8 *block) {}\n" "void Rte_Write_DUMMY_NVM_LIST_8_DUMMY_NVM_LIST_8(dt_DUMMY_NVM_LIST_8 *block) {}\n" "dt_DUMMY_NVM_LIST_16 *Rte_Pim_DUMMY_NVM_LIST_16(void) { return (dt_DUMMY_NVM_LIST_16 *)0; }\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_16_SetRamBlockStatus(UInt8 status) {}\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_16_GetErrorStatus(UInt8 *status) {}\n" - "void Rte_Call_PS_DUMMY_SwcNv_DUMMY_NVM_LIST_16_WriteBlock(dt_DUMMY_NVM_LIST_16 *block) {}\n" "void Rte_Read_DUMMY_NVM_LIST_16_DUMMY_NVM_LIST_16(dt_DUMMY_NVM_LIST_16 *block) {}\n" "void Rte_Write_DUMMY_NVM_LIST_16_DUMMY_NVM_LIST_16(dt_DUMMY_NVM_LIST_16 *block) {}\n" )